1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to the field of data transfer technology in memory.
2. Description of the Related Art
There are increasing demands for a semiconductor memory with improved integration density and speed as well as enhanced capacity. For example, a pseudo static RAM (PSRAM) for use in mobile phones is expected to reach the 256- to 512-Mbit size from the currently used 128-Mbit size. Conventionally, in order to meet the demands for enhanced capacity, improving the integration density enables reduction of memory chip area as well as improved speed in memory chips.
However, as the recent increase in integration density, wiring resistance also increases in chips, which has prohibited improvements in chip speed.
Therefore, Patent Document 1 (Japanese Patent Laid-Open No. 3222545) discloses an invention for improving speed of memory in chips. In the invention disclosed in Patent Document 1, plural memory cell brocks as sub-arrays are formed, and each system between each of the memory cell blocks and I/O terminals is independent from one another. That is, memory cell blocks A and B are formed and input/output terminals A and B are provided corresponding to each memory cell block. One system ranging from memory cell block A to an input/output terminal A, and another system ranging from memory cell block B to an input/output terminal B, are completely independent from each other. Only data input from the input/output terminal A can be written in the memory cell block A for writing data to the memory cell block A, and data can only be output to the input/output terminal A for reading data from the memory cell block A. Similarly, only data input from the input/output terminal B can be written in the memory cell block B for writing data to the memory cell block B, and data can only be output to the input/output terminal B for reading data from the memory cell block B.
As such, in the system of the invention described in Patent Document 1 has a following problem. Specifically, the system may be formed as a multi-chip package of a combination of a controller and memory. In this case, a pad used in memory may be changed depending on the type of controller. However, it is extremely difficult to change the pad being used due to the one-to-one correspondence between each memory cell block and each input/output terminal.